Multi-core processors are increasingly widespread and are used in many application domains to give performance gains where software processes are parallelized so that they run on multiple cores simultaneously. Each core may be thought of as part of a processor that performs reading and executing of instructions; for example, each core may be a central processing unit (CPU) within a single computing system. Generally speaking, single-core processors are able to process only one sequence of instructions at a time. A multi-core processor has two or more independent cores which may be provided in a single physical device such as a chip or chip package. The multiple cores may or may not have access to a shared physical memory although the present application is concerned with multi-core processors which do have a shared physical memory.
A shared physical memory or memories may be used to enable communication between the multiple cores and may be a block of random access memory (RAM) or other suitable memory. A hierarchy of caches is typically provided to speed up memory accesses from the cores to the memory. The cores, caches, and memory are typically connected to each other by use of an interconnect device. However, use of a shared physical memory in this way brings technical hurdles. For example, coherency between the various caches is typically maintained using a cache coherence protocol. However, cache coherency mechanisms are computationally expensive and use valuable interconnect resources.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known multi-core processors which use shared physical memory.